The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2006

Filed:

Feb. 15, 2005
Applicants:

Donald W. Brouillette, St. Albans, VT (US);

Thomas G. Ference, Essex Junction, VT (US);

Harold G Linde, Richmond, VT (US);

Michael S. Hibbs, Westford, VT (US);

Ronald L. Mendelson, Richmond, VT (US);

Inventors:

Donald W. Brouillette, St. Albans, VT (US);

Thomas G. Ference, Essex Junction, VT (US);

Harold G Linde, Richmond, VT (US);

Michael S. Hibbs, Westford, VT (US);

Ronald L. Mendelson, Richmond, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B24B 49/00 (2006.01); B24B 51/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.


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