The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2006
Filed:
Mar. 15, 2005
Priyavadan R. Patel, Chandler, AZ (US);
Chee-yee Chung, Chandler, AZ (US);
David G. Figueroa, Mesa, AZ (US);
Robert L. Sankman, Phoenix, AZ (US);
Yuan-liang LI, Chandler, AZ (US);
Hong Xie, Phoenix, AZ (US);
William P. Pinello, Phoenix, AZ (US);
Priyavadan R. Patel, Chandler, AZ (US);
Chee-Yee Chung, Chandler, AZ (US);
David G. Figueroa, Mesa, AZ (US);
Robert L. Sankman, Phoenix, AZ (US);
Yuan-Liang Li, Chandler, AZ (US);
Hong Xie, Phoenix, AZ (US);
William P. Pinello, Phoenix, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.