The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2006
Filed:
Oct. 12, 2001
Masashi Sahara, Hitachinaka, JP;
Fumiaki Endo, Hitachinaka, JP;
Masanori Kojima, Fussa, JP;
Katsuhiro Uchimura, Koganei, JP;
Hideaki Kanazawa, Hitachinaka, JP;
Masakazu Sugiura, Hitachi, JP;
Masashi Sahara, Hitachinaka, JP;
Fumiaki Endo, Hitachinaka, JP;
Masanori Kojima, Fussa, JP;
Katsuhiro Uchimura, Koganei, JP;
Hideaki Kanazawa, Hitachinaka, JP;
Masakazu Sugiura, Hitachi, JP;
Renesas Technology Corp., Tokyo, JP;
Hitachi ULSI Systems Co., Ltd., Tokyo, JP;
Abstract
In a high-performance semiconductor integrated circuit, the standby current is reduced by preventing current leakage in a semiconductor integrated circuit device, for example, the memory cell of an SRAM. A gate electrode G is formed on semiconductor substrateand n-type semiconductor regions(source/drain regions) are formed in the semiconductor substrate on both sides of this gate electrode. Within the same apparatus and under near-vacuum conditions, a depth of 2.5 nm or less is etched away from the surfaces of the source/drain regions and gate electrode, a film of Co is then formed on the source/drain regions, and thermal processing is applied to form CoSilayer. As a result, current leakage in the memory cell can be prevented and this method can be applied to semiconductor integrated circuit devices that have low current consumption or are battery-driven.