The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2006
Filed:
Oct. 18, 2004
Alper Ilkbahar, San Jose, CA (US);
Roy Scheuerlein, Cupertino, CA (US);
Andrew J. Walker, Mountain View, CA (US);
Luca Fasoli, San Jose, CA (US);
Alper Ilkbahar, San Jose, CA (US);
Roy Scheuerlein, Cupertino, CA (US);
Andrew J. Walker, Mountain View, CA (US);
Luca Fasoli, San Jose, CA (US);
Sandisk 3D LLC, Sunnyvale, CA (US);
Abstract
An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.