The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2006
Filed:
Dec. 09, 2003
Wagdi W. Abadeer, Jericho, VT (US);
Eric Adler, Jericho, VT (US);
Jeffrey S. Brown, Middlesex, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Jonathan M. Mckenna, Ann Arbor, MI (US);
Jed H. Rankin, South Burlington, VT (US);
Edward W. Sengle, Hinesburg, VT (US);
William R. Tonti, Essex Junction, VT (US);
Wagdi W. Abadeer, Jericho, VT (US);
Eric Adler, Jericho, VT (US);
Jeffrey S. Brown, Middlesex, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Jonathan M. McKenna, Ann Arbor, MI (US);
Jed H. Rankin, South Burlington, VT (US);
Edward W. Sengle, Hinesburg, VT (US);
William R. Tonti, Essex Junction, VT (US);
International Business Machines Corporation, Amonk, NY (US);
Abstract
A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.