The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2006

Filed:

Feb. 04, 2005
Applicants:

Akira Yamamoto, Mitaka, JP;

Konosuke Murakami, Mitaka, JP;

Yoshio Niki, Mitaka, JP;

Takashi Ishimoto, Mitaka, JP;

Yutaka Ueda, Mitaka, JP;

Inventors:

Akira Yamamoto, Mitaka, JP;

Konosuke Murakami, Mitaka, JP;

Yoshio Niki, Mitaka, JP;

Takashi Ishimoto, Mitaka, JP;

Yutaka Ueda, Mitaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01N 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention is a method for detecting float or peel of semiconductor chips arranged in X and Y axes directions diced and bonded to a dicing tape on a stage. The method includes detecting float or peel of the semiconductor chips in a respective horizontal or longitudinal row arranged in the X or Y axis direction; moving the stage in the X axis direction, the Y axis direction, a Z axis direction, and a rotational direction around the Z axis for aligning the stage with a position detection unit for detecting positions of the semiconductor chips in the X axis direction and the Y axis direction; detecting the positions of abnormal semiconductor chips in the respective horizontal or longitudinal row that includes said abnormal semiconductor chips; and specifying the positions of said abnormal semiconductor chips on the X-Y axes.


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