Integration scheme to improve nmos with poly cap while mitigating pmos degradation

Abstract

A method () fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes () on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown poly oxide layer (). Offset spacers are formed adjacent to sidewalls of the gate electrodes (). Extension regions are then formed () within the PMOS region and the NMOS region. Sidewall spacers are formed () adjacent to the sidewalls of the gate. electrodes. An n-type dopant is implanted into the NMOS region to form source/drain regions and a p-type dopant is implanted with an overdose amount into the PMOS region to form the source/drain regions within the PMOS region (). A poly cap layer is formed over the device () and an anneal or other thermal process is performed () that causes the p-type dopant to diffuse into the nitride containing cap oxide layer and obtain a selected dopant profile having sufficient lateral abruptness.