The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2006
Filed:
Nov. 30, 2004
Wen Jen Chiu, Hsinchu, TW;
Wei-chin Shiau, Hsin-Chu, TW;
Chen Hsin Hsiung, Taipei, TW;
Kuan Liang Wu, Taipei, TW;
Yu-jye Lan, Taipei, TW;
Shiaw-lin Chi, Hsinchu, TW;
Chia Hui Hsu, Hsin-Chu, TW;
Ming Tsang Yu, Taipei, JP;
Wen Jen Chiu, Hsinchu, TW;
Wei-Chin Shiau, Hsin-Chu, TW;
Chen Hsin Hsiung, Taipei, TW;
Kuan Liang Wu, Taipei, TW;
Yu-Jye Lan, Taipei, TW;
Shiaw-Lin Chi, Hsinchu, TW;
Chia Hui Hsu, Hsin-Chu, TW;
Ming Tsang Yu, Taipei, JP;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present invention provides an Intelligent Engineering Data Analysis (I-EDA) system and method to help prevent low wafer yield and prevent occurrences of abnormal events. The I-EDA has a non-conforming wafer tracing (NCWT) system that operates to correlate occurrences of abnormal events with low wafer yield. The method generally has the steps of performing a fabrication operation on wafers disposed within a wafer lot; determining if an abnormal event occurred while performing the fabrication operation on the wafers disposed within the wafer lot; using a NCWT to determine a statistical correlation between an occurrence of an abnormal event and a wafer yield of the wafers being processed during the occurrence of the abnormal event if the abnormal event occurred during processing of the wafers disposed within the wafer lot; and using the determined statistical correlation to analyze the fabrication process and thereby improve wafer yield.