The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2006
Filed:
Sep. 24, 2004
Stanford W. Crane, Jr., San Jose, CA (US);
Zsolt Horvath, Millbrae, CA (US);
Josh Nickel, San Jose, CA (US);
Myoung-soo Jeon, Fremont, CA (US);
Charley Ogata, San Jose, CA (US);
Vincent Alcaria, Manteca, CA (US);
Patrick Codd, Palo Alto, CA (US);
Stanford W. Crane, Jr., San Jose, CA (US);
Zsolt Horvath, Millbrae, CA (US);
Josh Nickel, San Jose, CA (US);
Myoung-soo Jeon, Fremont, CA (US);
Charley Ogata, San Jose, CA (US);
Vincent Alcaria, Manteca, CA (US);
Patrick Codd, Palo Alto, CA (US);
Silicon Bandwidth, Inc., San Jose, CA (US);
Abstract
A capacitor structure may be incorporated into an interposer or substrate associated with an IC chip to stabilize the input/output signals, such as power and ground, between the IC chip and a printed circuit board. In accordance with one embodiment, the capacitor structure may include a plurality of individual capacitors connected together to form a monolithic capacitor blade having a length, width, and height, wherein each of the length and height of the blade spans multiple of the individual capacitors. The blade includes multiple electrical conductive paths extending the height of the capacitor blade. According to another embodiment, the capacitor structure includes multiple interleaved power and ground layers separated by insulating layers. The power layers connect to power leads and the ground layers connect to ground leads.