The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2006
Filed:
Apr. 28, 2004
Jung-chih Tsao, Taipei, TW;
Chi-wen Liu, Hsinchu, TW;
Si-kua Cheng, Hsinchu, TW;
Che-tsao Wang, Taipei, TW;
Steven Lin, Hsin-Chu, TW;
Hsien-ping Feng, Yonghe, TW;
Chen-peng Fan, Hsinchu, TW;
Jung-Chih Tsao, Taipei, TW;
Chi-Wen Liu, Hsinchu, TW;
Si-Kua Cheng, Hsinchu, TW;
Che-Tsao Wang, Taipei, TW;
Steven Lin, Hsin-Chu, TW;
Hsien-Ping Feng, Yonghe, TW;
Chen-Peng Fan, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.