The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2006
Filed:
Dec. 28, 2004
Hisashi Tanie, Tsuchiura, JP;
Nae Hisano, Matsudo, JP;
Hiroyuki Ohta, Tsuchiura, JP;
Hiroaki Ikeda, Tokyo, JP;
Ichiro Anjo, Tokyo, JP;
Mitsuaki Katagiri, Tokyo, JP;
Yuji Watanabe, Tokyo, JP;
Hisashi Tanie, Tsuchiura, JP;
Nae Hisano, Matsudo, JP;
Hiroyuki Ohta, Tsuchiura, JP;
Hiroaki Ikeda, Tokyo, JP;
Ichiro Anjo, Tokyo, JP;
Mitsuaki Katagiri, Tokyo, JP;
Yuji Watanabe, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an 'Si' interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.