The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2006

Filed:

Feb. 20, 2002
Applicants:

Shinya Miyazaki, Maebaru, JP;

Kei Katoh, Tokyo, JP;

Koudoh Yamauchi, Fukuoka, JP;

Inventors:

Shinya Miyazaki, Maebaru, JP;

Kei Katoh, Tokyo, JP;

Koudoh Yamauchi, Fukuoka, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit has nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors. Therefore, the bit line potential can be varied by word line selection.


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