The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2006
Filed:
Aug. 02, 2005
Gary R. Janik, Palo Alto, CA (US);
Eric Bouche, Pleasanton, CA (US);
Gary R. Janik, Palo Alto, CA (US);
Eric Bouche, Pleasanton, CA (US);
KLA-Tencor Technologies Corporation, Milpitas, CA (US);
Abstract
A method for measuring three-dimensional gate dielectric structures can involve forming test patterns that cover a range of dimensional values for the fins on which the gate dielectric structures are formed. Then, by measuring the gate dielectric properties and then correlating those measurements with the underlying fin dimensions, a relationship between fin dimension(s) and gate dielectric properties can be determined. That relationship can then be applied to actual device structures to interpolate/extrapolate gate dielectric property values based on the fin dimensions in the actual device.