The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2006

Filed:

Jan. 26, 2006
Applicants:

Junichi Tanaka, Tsuchiura, JP;

Hideyuki Yamamoto, Kudamatsu, JP;

Shoji Ikuhara, Hikari, JP;

Akira Kagoshima, Kudamatsu, JP;

Inventors:

Junichi Tanaka, Tsuchiura, JP;

Hideyuki Yamamoto, Kudamatsu, JP;

Shoji Ikuhara, Hikari, JP;

Akira Kagoshima, Kudamatsu, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Occurrence of a process abnormality in a semiconductor processing apparatus is obtained by obtaining an index of a processing size of each of wafers within an X-th lot, in which the X represents an integer, based on data obtained during processing of each of the wafers of the X-th lot, obtaining an index of a processing size of each of wafers within an X+1-th lot, based on data thereof and anticipating an index of a processing sizes of each of wafers within an X+2-th lot, based on the index obtained as to each of the wafers of the X-th lot and the X+1-th lot. A process abnormality occurring during the processing of a wafer of the X+2-th lot is anticipated when the anticipated index of the X+2-th lot exceeds an allowance range.


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