The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2006

Filed:

Oct. 10, 2005
Applicants:

Warren M. Farnworth, Nampa, ID (US);

Dale W. Collins, Boise, ID (US);

Steven M. Mcdonald, Star, ID (US);

Inventors:

Warren M. Farnworth, Nampa, ID (US);

Dale W. Collins, Boise, ID (US);

Steven M. McDonald, Star, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/053 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.


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Farnworth, Warren. (2006). Semiconductor assemblies having electrophoretically insulated vias (U.S. Patent No. 7105921). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7105921

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