The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2006

Filed:

Dec. 07, 2004
Applicants:

Srikanteswara Dakshina-murthy, Wappinger Falls, NY (US);

Douglas Bonser, Hopewell Junction, NY (US);

Hans Van Meer, Fishkill, NY (US);

David Brown, Pleasant Valley, NY (US);

Inventors:

Srikanteswara Dakshina-Murthy, Wappinger Falls, NY (US);

Douglas Bonser, Hopewell Junction, NY (US);

Hans Van Meer, Fishkill, NY (US);

David Brown, Pleasant Valley, NY (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

Gate electrodes with selectively tuned channel thicknesses are formed by selective epitaxial growth. Embodiments include forming shallow trench isolation regions in an SOI substrate, selectively removing the nitride stop layer and pad oxide layer in an exposed particular active region, and implementing selective epitaxial growth to increase the thickness of the semiconductor layer in the particular active region. Subsequently, the remaining nitride stop and pad oxide layers in other active regions are removed, gate dielectric layers formed, as by thermal oxidation, and the transistors completed.


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