The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2006

Filed:

Jul. 21, 2004
Applicants:

Uei-ming Jow, Tai Chung, TW;

Ying-jiunn Lai, Ping Tung Hsien, TW;

Chun-kun Wu, Yun Lin Hsien, TW;

Pel-shen Wei, Yungho, TW;

Chang-sheng Chen, Taipei, TW;

Ching-liang Weng, Taipei, TW;

Inventors:

Uei-Ming Jow, Tai Chung, TW;

Ying-Jiunn Lai, Ping Tung Hsien, TW;

Chun-Kun Wu, Yun Lin Hsien, TW;

Pel-Shen Wei, Yungho, TW;

Chang-Sheng Chen, Taipei, TW;

Ching-Liang Weng, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 4/06 (2006.01); H01G 4/08 (2006.01); H01G 4/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention describes an intermediate for use in a capacitive printed circuit board (PCB), which relates to a capacitive apparatus and manufacturing method for a built-in capacitor with a non-symmetrical electrode used to reduce inaccuracy of the error compression alignment on laminates. The invention employs a plurality of different sized metal laminates stacked for a built-in capacitor to achieve a high-precise capacitor PCB. More particularly, the invention can raise the capability of noise-immunity of a capacitive PCB applied to high frequency/speed modules and systems, and also provides precise capacitance to regular circuit design for the need of compact package and high-precise capacitance in the future.


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