The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2006
Filed:
Oct. 15, 2003
Hsiang-fan Lee, Hsin-Chu, TW;
Shih-wei Wang, Hsin-Chu, TW;
Yi-jiun Lin, Taipei, TW;
Kuo-wei Chu, Hsin-Chu, TW;
Ching-sen Kuo, Taipei, TW;
Chia-tong Ho, Hsin-Chu, TW;
Hsiang-Fan Lee, Hsin-Chu, TW;
Shih-Wei Wang, Hsin-Chu, TW;
Yi-Jiun Lin, Taipei, TW;
Kuo-Wei Chu, Hsin-Chu, TW;
Ching-Sen Kuo, Taipei, TW;
Chia-Tong Ho, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin Chu, TW;
Abstract
A method for forming triple polysilicon split gate electrodes in a EEPROM flash memory array providing a first gate structure; blanket depositing a first polysilicon layer over the first gate structure; etching back the first polysilicon layer according to a first dry etching process; blanket depositing a second dielectric insulating layer over the first polysilicon layer; blanket depositing a second polysilicon layer over the second dielectric insulating layer; and, lithographically patterning and dry etching according to a respective third and fourth dry etching process through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.