The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2006
Filed:
Nov. 05, 2003
Tze Ho Simon Chan, Singapore, SG;
Mousumi Bhat, Singapore, SG;
Jeffrey Chee, Singapore, SG;
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Abstract
A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.