The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2006
Filed:
Jan. 06, 2004
Yisuo LI, Singapore, SG;
Francis Benistant, San Jose, CA (US);
Kian Meng Tee, Singapore, SG;
King Jien Chui, Singapore, SG;
Yisuo Li, Singapore, SG;
Francis Benistant, San Jose, CA (US);
Kian Meng Tee, Singapore, SG;
King Jien Chui, Singapore, SG;
Chartered Semiconductor Manufacturing L.T.D., Singapore, SG;
Abstract
A method for forming elevated source/drain regions. A gate structure is formed over a substrate. The substrate comprised of silicon. We form a polysilicon layer preferably using PVD or CVD over the gate structure and the substrate. A poly/Si interface is formed between the polysilicon layer and the substrate. We perform a poly/Si interface amorphization implant to amorphize at least the poly/Si interface in the S/D areas and to from an amorphous region. We anneal the substrate to crystallize the amorphous region and the polysilicon layer over the amorphous region to form an elevated silicon region in the source/drain area. Next, source/drain regions in are formed in the elevated silicon regions and the substrate.