The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2006
Filed:
Jul. 27, 2004
Zvi Or-bach, San Jose, CA (US);
Petrica Avram, Iasi, RO;
Romeo Iacobut, Iasi, RO;
Adrian Apostol, Iasi, RO;
Ze'ev Wurman, Palo Alto, CA (US);
Adam Leventhal, Redwood City, CA (US);
Richard Zeman, San Jose, CA (US);
Zvi Or-Bach, San Jose, CA (US);
Petrica Avram, Iasi, RO;
Romeo Iacobut, Iasi, RO;
Adrian Apostol, Iasi, RO;
Ze'ev Wurman, Palo Alto, CA (US);
Adam Leventhal, Redwood City, CA (US);
Richard Zeman, San Jose, CA (US);
eASIC Corporation, Santa Clara, CA (US);
Abstract
A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.