The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2006

Filed:

Jul. 14, 2003
Applicants:

OM P. Agrawal, Los Altos, CA (US);

Bai Nguyen, Union City, CA (US);

Kuang Chi, San Jose, CA (US);

Brad Sharpe-geisler, San Jose, CA (US);

Giap Tran, San Jose, CA (US);

Inventors:

Om P. Agrawal, Los Altos, CA (US);

Bai Nguyen, Union City, CA (US);

Kuang Chi, San Jose, CA (US);

Brad Sharpe-Geisler, San Jose, CA (US);

Giap Tran, San Jose, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); H03K 19/173 (2006.01); H03K 19/177 (2006.01); H03K 19/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods are disclosed to provide programmable input/output functionality for a programmable logic device. For example, in accordance with one embodiment of the present invention, a programmable interface selectively employs a scalable serializer-deserializer and clock and data recovery circuit. The programmable interface further includes programmable input/output buffers and embedded memory to allow the programmable logic device to support a wide range of input/output interface standards.


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