The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2006
Filed:
Feb. 24, 2005
Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
Brian E. Hornung, Richardson, TX (US);
Jong Yoon, Plano, TX (US);
Deborah J. Riley, Richardson, TX (US);
Amitava Chatterjee, Plano, TX (US);
Brian E. Hornung, Richardson, TX (US);
Jong Yoon, Plano, TX (US);
Deborah J. Riley, Richardson, TX (US);
Amitava Chatterjee, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The present invention provides, in one embodiment, a method of fabricating a semiconductor device (). In one embodiment, the method includes growing an oxide layerfrom a substrateover a first dopant regionand a second dopant region, implanting a first dopant through the oxide layer, into the substratein the first dopant region, and adjacent a gate structure, and substantially removing the oxide layerfrom the substrate within the second dopant region. Subsequent to the removal of the oxide layerin the second dopant region, a second dopant that is opposite in type to the first dopant is implanted into the substrateand within the second dopant regionand adjacent a gate structure