The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2006
Filed:
Aug. 18, 2004
Kuo-chyuan Tzeng, Hsin-Chu, TW;
Ming-hsiang Chiang, Taipei, TW;
Wen-chuan Chiang, Hsin-Chu, TW;
Dennis J. Sinitsky, Sunnyvale, CA (US);
Kuo-Chyuan Tzeng, Hsin-Chu, TW;
Ming-Hsiang Chiang, Taipei, TW;
Wen-Chuan Chiang, Hsin-Chu, TW;
Dennis J. Sinitsky, Sunnyvale, CA (US);
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.