The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7084489 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 01, 2006

Filed:

Aug. 18, 2004
Applicant:

Blaine J. Thurgood, Nampa, ID (US);

Inventor:

Blaine J. Thurgood, Nampa, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

Stress balanced semiconductor device packages, a method of forming, and a method of modifying a mold segment for use in the method are disclosed. A semiconductor die is attached to one side of a substrate having discrete conductive elements such as a ball grid array (BGA) on the opposing side thereof. An envelope of encapsulant material is disposed over the semiconductor die on one side of the substrate while a stress balancing structure comprising at least one stem member and at least one transversely extending branch member formed of encapsulant material is disposed over the opposing side of the substrate in an arrangement which does not interfere with the discrete conductive elements. The envelope and the stress balancing structure may be simultaneously formed.


Find Patent Forward Citations

Thurgood, Blaine. (2006). Computer system including at least one stress balanced semiconductor package (U.S. Patent No. 7084489). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7084489

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