Semiconductor device having memory and logic devices with reduced resistance and leakage current

Abstract

A semiconductor technique is provided which can achieve both of lowered resistance in a logic formation region and reduced leakage current of the capacitor of a memory device. Source/drain regions () are formed in the upper surface of a semiconductor substrate () in a memory formation region and cobalt silicide films () are formed in the upper surfaces of the source/drain regions (). Source/drain regions () are formed in the upper surface of the semiconductor substrate () in a logic formation region and cobalt silicide films () are formed in the upper surfaces of the source/drain regions (). The cobalt silicide films () in the logic formation region are thicker than the cobalt silicide films () in the memory formation region.