The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2006
Filed:
Jan. 30, 2004
Andrew D. Bailey, Iii, Pleasanton, CA (US);
Michael Ravkin, Sunnyvale, CA (US);
Mikhail Korolik, San Jose, CA (US);
Puneet Yadav, Fremont, CA (US);
Andrew D. Bailey, III, Pleasanton, CA (US);
Michael Ravkin, Sunnyvale, CA (US);
Mikhail Korolik, San Jose, CA (US);
Puneet Yadav, Fremont, CA (US);
Lam Research Corporation, Fremont, CA (US);
Abstract
A system and method for planarizing and controlling non-uniformity on a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple features in the pattern. The conductive interconnect material having an overburden portion. A bulk of the overburden portion is removed and a remaining portion of the overburden portion has a non-uniformity. The non-uniformity is mapped, optimal solution determined and a dynamic liquid meniscus etch process recipe is developed to correct the non-uniformity. A dynamic liquid meniscus etch process, using the dynamic liquid meniscus etch process recipe, is applied to correct the non-uniformity to substantially planarize the remaining portion of the overburden portion.