The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2006
Filed:
Jun. 06, 2003
Lawrence Bauer, Jr., Pine Bush, NY (US);
Kenneth Giewont, Hopewell Junction, NY (US);
Subramanian Iyer, Mount Kisco, NY (US);
Bosang Kim, Mount Vernon, NY (US);
Jeffrey Lloyd, Poughkeepsie, NY (US);
Peter Locke, Hopewell Junction, NY (US);
James Norum, Brewster, NY (US);
Paul Parries, Wappingers Falls, NY (US);
Kent Way, Poughkeepsie, NY (US);
Kwong Hon Wong, Wappingers Falls, NY (US);
Lawrence Bauer, Jr., Pine Bush, NY (US);
Kenneth Giewont, Hopewell Junction, NY (US);
Subramanian Iyer, Mount Kisco, NY (US);
Bosang Kim, Mount Vernon, NY (US);
Jeffrey Lloyd, Poughkeepsie, NY (US);
Peter Locke, Hopewell Junction, NY (US);
James Norum, Brewster, NY (US);
Paul Parries, Wappingers Falls, NY (US);
Kent Way, Poughkeepsie, NY (US);
Kwong Hon Wong, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The integrity of a liner in an interconnect structure or other layer in an integrate circuit is tested in a short time by exposing the liner to a reactive gas that attacks the underlying silicon or other material behind the liner. A weak spot in the liner permits the gas to react with the silicon, which produces a visible area that can be readily identified. The test can be performed in a few hours, in contrast to a period of several months required to complete the process, package the circuit and conduct a burn-in test.