The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2006
Filed:
Jan. 20, 2004
Joong S. Jeon, Cupertino, CA (US);
Robert B. Clark-phelps, Northborough, MA (US);
Qi Xiang, San Jose, CA (US);
Huicai Zhong, Wappinger Falls, NY (US);
Joong S. Jeon, Cupertino, CA (US);
Robert B. Clark-Phelps, Northborough, MA (US);
Qi Xiang, San Jose, CA (US);
Huicai Zhong, Wappinger Falls, NY (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a buffer layer on the substrate, where the buffer layer comprises ALD silicon dioxide. The buffer layer can be formed by utilizing a silicon tetrachloride precursor in an atomic layer deposition process, for example. The buffer layer comprises substantially no pin-hole defects and may have a thickness, for example, that is less than approximately 5.0 Angstroms. The method further comprises forming a high-k dielectric layer over the buffer layer. The high-k dielectric layer may be, for example, hafnium oxide, zirconium oxide, or aluminum oxide. According to this exemplary embodiment, the method further comprises forming a gate electrode layer over the high-k dielectric layer. The gate electrode layer may be polycrystalline silicon, for example.