The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2006
Filed:
Sep. 22, 2004
Dina H. Triyoso, Austin, TX (US);
Olubunmi O. Adetutu, Austin, TX (US);
Randy W. Cotton, Pflugerville, TX (US);
Dina H. Triyoso, Austin, TX (US);
Olubunmi O. Adetutu, Austin, TX (US);
Randy W. Cotton, Pflugerville, TX (US);
Freescale Semiconductor, Inc, Austin, TX (US);
Abstract
A method for forming a semiconductor device () creates a dielectric layer () with high dielectric constant. An interfacial layer () is formed over a semiconductor substrate (). A dielectric layer () is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions () within the semiconductor substrate.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile