The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2006
Filed:
Jun. 26, 2003
Vigyan Singhal, Fremont, CA (US);
Joseph E. Higgins, Albany, CA (US);
Chung-wah Norris Ip, Fremont, CA (US);
Howard Wong-toi, Albany, CA (US);
Vigyan Singhal, Fremont, CA (US);
Joseph E. Higgins, Albany, CA (US);
Chung-Wah Norris Ip, Fremont, CA (US);
Howard Wong-Toi, Albany, CA (US);
Jasper Design Automation, Inc., Mountain view, CA (US);
Abstract
The present invention is used for guiding formal verification of a circuit design in circuit simulation software to optimize the time required for verification of a circuit design. The invention modifies the analysis region being used for verification in order to optimize the time for verification. The invention allows for manual, semi-automatic, and automatic modification of the analysis region. The modification is done by either expanding or reducing the analysis region or by adding new rules as assumptions to the existing analysis region. The invention also uses the concept of an articulation point for modification of the analysis region. The modification of the analysis region is performed in a manner to optimize time and memory required for verification of the circuit design.