The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2006
Filed:
Jun. 13, 2003
Kong-beng Thei, Hsin-Chu, TW;
Chun-lung Cheng, Tu-Chen, TW;
His-chien Lin, Hsin-Chu, TW;
Li-don Chen, Hsin-Chu, TW;
Tung-lung Lai, Hsin-Chu, TW;
Chi-lung Lin, Hsin-Chu, TW;
Kong-Beng Thei, Hsin-Chu, TW;
Chun-Lung Cheng, Tu-Chen, TW;
His-Chien Lin, Hsin-Chu, TW;
Li-Don Chen, Hsin-Chu, TW;
Tung-Lung Lai, Hsin-Chu, TW;
Chi-Lung Lin, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
An improved barrier layer stack and method for forming the same for preserving an aluminum alloy interconnect resistivity, the method comprising providing a semiconductor process wafer comprising an exposed conductive region; forming a first barrier layer comprising a barrier layer stack over the exposed conductive region comprising one of a TiN or Ti layer in contact with the conductive region; forming at least one additional barrier layer comprising the barrier layer stack to form an alternating sequence of TiN and Ti layers; forming an uppermost barrier layer of TiN comprising the barrier layer stack; forming an overlying aluminum alloy region in contact with the uppermost barrier layer; and, subjecting the semiconductor process wafer to at least one process comprising a temperature of greater than temperatures greater than about 350° C.