The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2006
Filed:
May. 12, 2004
OM Agrawal, Los Altos, CA (US);
Giap Tran, San Jose, CA (US);
Bai Nguyen, Union City, CA (US);
Kiet Truong, San Jose, CA (US);
Om Agrawal, Los Altos, CA (US);
Giap Tran, San Jose, CA (US);
Bai Nguyen, Union City, CA (US);
Kiet Truong, San Jose, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Programmable devices, such as FPGAs, are designed with I/O buffer architectures having (at least) three different types of I/O buffers: single-ended buffers with Peripheral Component Interconnect (PCI) clamps, single-ended buffers without PCI clamps, and differential buffers without PCI clamps. By distributing these different types of I/O buffers around the periphery of the device, a relatively low-cost device can be implemented with relatively small I/O buffers that collectively provide all of the I/O signaling functionality of prior-art devices that are implemented with relatively large, all-purpose I/O buffers, each of which supports the full range of I/O signaling options available on the device.