The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2006
Filed:
Sep. 09, 2003
Micha Gutman, Migdal Haemek, IL;
Yakov Roizin, Afula, IL;
Menachem Vofsy, Migdal Haemek, IL;
Efraim Aloni, Migdal Haemek, IL;
Avi Ben-gigi, Migdal haemek, IL;
Fumihiko Noro, Kyoto, JP;
Masatoshi Arai, Kyoto, JP;
Nobuyoshi Takahashi, Kyoto, JP;
Koji Yoshida, Kyoto, JP;
Micha Gutman, Migdal Haemek, IL;
Yakov Roizin, Afula, IL;
Menachem Vofsy, Migdal Haemek, IL;
Efraim Aloni, Migdal Haemek, IL;
Avi Ben-Gigi, Migdal haemek, IL;
Fumihiko Noro, Kyoto, JP;
Masatoshi Arai, Kyoto, JP;
Nobuyoshi Takahashi, Kyoto, JP;
Koji Yoshida, Kyoto, JP;
Tower Semiconductor Ltd., Migdal Haemek, IL;
Abstract
A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.