The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2006
Filed:
Dec. 02, 2003
Jong-hyun Choi, Suwon, KR;
Jae-hoon Kim, Suwon, KR;
Jun-hyung Kim, Yongin, KR;
Chi-wook Kim, Kyungki-do, KR;
Han-gu Sohn, Suwon, KR;
Jong-hyun Choi, Suwon, KR;
Jae-hoon Kim, Suwon, KR;
Jun-hyung Kim, Yongin, KR;
Chi-wook Kim, Kyungki-do, KR;
Han-gu Sohn, Suwon, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
Provided are a reference voltage generating circuit and an internal voltage generating circuit for controlling an internal voltage level, where the reference voltage generating circuit includes a distributing unit, a clamping control unit, and a control unit; the distributing unit has a voltage level lower than that of an external power supply voltage in response to the external power supply voltage, and outputs via an output terminal a reference voltage which varies according to an operating mode; the clamping control unit is connected between the output terminal and a ground voltage, and clamps the voltage level of the reference voltage at a constant level in response to a control voltage having a voltage level which is lower than that of the reference voltage; the control unit increases or decreases the voltage level of the reference voltage in response to first and second operating mode signals; the control unit includes a first control transistor and a second control transistor; and the reference voltage generating circuit controls a reference voltage level according to an operating mode of the semiconductor memory device such that the operating characteristics of the semiconductor memory device can be improved in some operating modes and power dissipation can be minimized in other operating modes.