The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2006

Filed:

Aug. 27, 2003
Applicants:

Satoru Yamada, Tokyo, JP;

Ryo Nagai, Tokyo, JP;

Kiyonori Oyu, Tokyo, JP;

Ryoichi Nakamura, Tokyo, JP;

Norikatsu Takaura, Tokyo, JP;

Inventors:

Satoru Yamada, Tokyo, JP;

Ryo Nagai, Tokyo, JP;

Kiyonori Oyu, Tokyo, JP;

Ryoichi Nakamura, Tokyo, JP;

Norikatsu Takaura, Tokyo, JP;

Assignees:

Elpida Memory, Inc., Tokyo, JP;

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.


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