The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2006
Filed:
Apr. 30, 1999
David R. Hembree, Boise, ID (US);
Salman Akram, Boise, ID (US);
Warren M. Farnworth, Nampa, ID (US);
Alan G. Wood, Boise, ID (US);
James M. Wark, Boise, ID (US);
Derek Gochnour, Boise, ID (US);
David R. Hembree, Boise, ID (US);
Salman Akram, Boise, ID (US);
Warren M. Farnworth, Nampa, ID (US);
Alan G. Wood, Boise, ID (US);
James M. Wark, Boise, ID (US);
Derek Gochnour, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact members, configured to electrically contact corresponding contact locations on the die. The interconnect also includes a pattern of conductors formed separately from the substrate, and then bonded to the substrate, in electrical communication with the contact members. The conductors can be mounted to a multi layered tape similar to TAB tape, or alternately bonded directly to the substrate. In addition, each conductor can include an opening aligned with a corresponding contact member, and filled with a conductive material, such as a conductive adhesive or solder. The conductive material electrically connects the contact members and conductors, and provides an expansion joint to allow expansion of the conductors without stressing the contact members. Also provided are a system for testing dice that includes the interconnect, and a system for testing wafers wherein the interconnect is formed as a probe card.