The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2006

Filed:

Jun. 29, 2005
Applicants:

Michiharu Matsui, Fujisawa, JP;

Seiichi Mori, Tokyo, JP;

Riichiro Shirota, Fujisawa, JP;

Yuji Takeuchi, Yokohama, JP;

Takeshi Kamigaichi, Yokohama, JP;

Inventors:

Michiharu Matsui, Fujisawa, JP;

Seiichi Mori, Tokyo, JP;

Riichiro Shirota, Fujisawa, JP;

Yuji Takeuchi, Yokohama, JP;

Takeshi Kamigaichi, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device of a selective gate region having a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating film, and an element isolating region including an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer. The element isolating region isolates an element region and is self-aligned with the first electrode layer, a second insulating film is formed on the first electrode layer and the element isolating region, and an open portion exposes a surface of the first electrode layer and is formed in the second insulating film. A second electrode layer is formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.


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