The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2006
Filed:
Nov. 19, 2002
Fumio Ootsuka, Tokorozawa, JP;
Takahiro Onai, Ome, JP;
Kazuhiro Ohnishi, Kodaira, JP;
Shoji Wakahara, Yokohama, JP;
Fumio Ootsuka, Tokorozawa, JP;
Takahiro Onai, Ome, JP;
Kazuhiro Ohnishi, Kodaira, JP;
Shoji Wakahara, Yokohama, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
Provided is a manufacturing method of a semiconductor device which comprises forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer of a pocket structure, the device of the present invention is suppressed in fluctuations in the threshold voltage. Moreover, with a relative increase in the controllable width of a depletion layer, a sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve a switching rate of the MISFET.