The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2006
Filed:
Mar. 28, 2002
Jeff Rearick, Ft Collins, CO (US);
Manish Sharma, Fort Collins, CO (US);
Jeff Rearick, Ft Collins, CO (US);
Manish Sharma, Fort Collins, CO (US);
Other;
Abstract
A method and apparatus for generating test patterns used to test an integrated circuit (IC). The apparatus comprises first logic for determining a subset of transition fault sites on an IC to be tested, second logic that identifies a longest sensitizable path through each transition fault site of the subset of transition fault sites, and third logic that generates a bounded set of test patterns that test the identified longest sensitizable paths through each transition fault site of the subset of transition fault sites. The present invention combines various aspects of transition fault modeling and path delay fault modeling to enable global delay testing of an IC within reasonable amount of time.