The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2006
Filed:
Apr. 23, 2004
Masahiko Ogino, Hitachi, JP;
Shuji Eguchi, Ibaraki-ken, JP;
Akira Nagai, Hitachi, JP;
Takumi Ueno, Mito, JP;
Masanori Segawa, Hitachi, JP;
Hiroyoshi Kokaku, Hitachi, JP;
Toshiaki Ishii, Hitachi, JP;
Ichiro Anjoh, Koganei, JP;
Asao Nishimura, Kokubunji, JP;
Chuichi Miyazaki, Akishima, JP;
Mamoru Mita, Hitachi, JP;
Norio Okabe, Hitachi, JP;
Masahiko Ogino, Hitachi, JP;
Shuji Eguchi, Ibaraki-ken, JP;
Akira Nagai, Hitachi, JP;
Takumi Ueno, Mito, JP;
Masanori Segawa, Hitachi, JP;
Hiroyoshi Kokaku, Hitachi, JP;
Toshiaki Ishii, Hitachi, JP;
Ichiro Anjoh, Koganei, JP;
Asao Nishimura, Kokubunji, JP;
Chuichi Miyazaki, Akishima, JP;
Mamoru Mita, Hitachi, JP;
Norio Okabe, Hitachi, JP;
Hitachi Cable, Ltd., Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
In a semiconductor device having a three-layered buffer layer comprising core layerhaving interconnected foams such as a three-dimensional reticular structure and adhesive layersprovided on both sides of the core layer as a stress buffer layer between semiconductor chipand wiringto lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layerto total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.