The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2006

Filed:

Jan. 21, 2003
Applicants:

Tom E. Pearson, Beaverton, OR (US);

Carolyn R. Mccormick, Hillsboro, OR (US);

Jayne L. Mershon, Portland, OR (US);

Inventors:

Tom E. Pearson, Beaverton, OR (US);

Carolyn R. McCormick, Hillsboro, OR (US);

Jayne L. Mershon, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.


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