The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2006
Filed:
Nov. 19, 2003
Robert J. Mears, Wellesley, MA (US);
Jean Augustin Chan Sow Fook Yiptong, Waltham, MA (US);
Marek Hytha, Brookline, MA (US);
Scott A. Kreps, Southborough, MA (US);
Ilija Dukovski, Newton, MA (US);
Robert J. Mears, Wellesley, MA (US);
Jean Augustin Chan Sow Fook Yiptong, Waltham, MA (US);
Marek Hytha, Brookline, MA (US);
Scott A. Kreps, Southborough, MA (US);
Ilija Dukovski, Newton, MA (US);
RJ Mears, LLC, Waltham, MA (US);
Abstract
A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.