The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Aug. 27, 2004
Noriyoshi Watanabe, Chitose, JP;
Noriaki Maeda, Fussa, JP;
Masanao Yamaoka, Hachioji, JP;
Yoshihiro Shinozaki, Fukuoka, JP;
Noriyoshi Watanabe, Chitose, JP;
Noriaki Maeda, Fussa, JP;
Masanao Yamaoka, Hachioji, JP;
Yoshihiro Shinozaki, Fukuoka, JP;
Renesas Technology Corp, Tokyo, JP;
SuperH, Inc., San Jose, CA (US);
Renesas Northern Japan Semiconductor, Inc., Hokkaido, JP;
Hitachi ULSI Systems Co., Ltd., Tokyo, JP;
Abstract
A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.