The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2006

Filed:

Jul. 11, 2002
Applicants:

Peir Chu, Portland, OR (US);

Steve Schiveley, Forest Grove, OR (US);

Aaron J. Steyskal, Portland, OR (US);

Mike Greenwood, Oregon City, OR (US);

Tao Liu, University Place, WA (US);

Inventors:

Peir Chu, Portland, OR (US);

Steve Schiveley, Forest Grove, OR (US);

Aaron J. Steyskal, Portland, OR (US);

Mike Greenwood, Oregon City, OR (US);

Tao Liu, University Place, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A user-selectable integrated circuit capacitance apparatus may include first and second electrodes defining a first fractal geometry, along with second and third electrodes defining a second fractal geometry. A dielectric may be located adjacent to the first and third electrodes. A method of fabricating the apparatus may include selecting a dielectric layer, forming the first and second electrodes so as to define the first fractal geometry on the dielectric layer, and then forming third and fourth electrodes so as to define a second fractal geometry on the dielectric layer. A circuit package may include external package connections connected to the electrodes of the apparatus. A system may include the apparatus coupled to a wireless transceiver by way of a power supply trace.


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