The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Mar. 30, 2004
Hsien-ping Feng, Yonghe, TW;
Jung-chih Tsao, Taipei, TW;
Hsi-kuei Cheng, Hsinchu, TW;
Chih-tsung Lee, Hsinchu, TW;
Ming-yuan Cheng, Taipei, TW;
Steven Lin, Shih-Chu, TW;
Ray Chuang, Hsin Chu, TW;
Chi-wen Liu, Hsinchu, TW;
Hsien-Ping Feng, Yonghe, TW;
Jung-Chih Tsao, Taipei, TW;
Hsi-Kuei Cheng, Hsinchu, TW;
Chih-Tsung Lee, Hsinchu, TW;
Ming-Yuan Cheng, Taipei, TW;
Steven Lin, Shih-Chu, TW;
Ray Chuang, Hsin Chu, TW;
Chi-Wen Liu, Hsinchu, TW;
Abstract
A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cmcurrent density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a Hplasma treatment. A second ECP process with a first deposition step at a 40 mA/cmcurrent density and second deposition step at a 60 mA/cmcurrent density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.