The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Apr. 19, 2004
Olubunmi O. Adetutu, Austin, TX (US);
Lynne M. Michaelson, Austin, TX (US);
Kathleen C. Yu, Austin, TX (US);
Robert E. Jones, Jr., Austin, TX (US);
Olubunmi O. Adetutu, Austin, TX (US);
Lynne M. Michaelson, Austin, TX (US);
Kathleen C. Yu, Austin, TX (US);
Robert E. Jones, Jr., Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.