The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Jul. 21, 2004
Song Zhao, Plano, TX (US);
Sue E. Crank, Coppell, TX (US);
Amitava Chatterjee, Plano, TX (US);
Kaiping Liu, Plano, TX (US);
Jiong-ping LU, Richardson, TX (US);
Donald S. Miles, Plano, TX (US);
Duofeng Yue, Plano, TX (US);
Lance S. Robertson, Rockwall, TX (US);
Song Zhao, Plano, TX (US);
Sue E. Crank, Coppell, TX (US);
Amitava Chatterjee, Plano, TX (US);
Kaiping Liu, Plano, TX (US);
Jiong-Ping Lu, Richardson, TX (US);
Donald S. Miles, Plano, TX (US);
Duofeng Yue, Plano, TX (US);
Lance S. Robertson, Rockwall, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method for forming metal silicide regions in source and drain regions () is described. Prior to the thermal annealing of the source and drain regions (), germanium is implanted into a semiconductor substrate adjacent to sidewall structures () formed adjacent gate structures (). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (). Following thermal annealing of the source and drain regions (), the implanted germanium prevents the formation of metal silicide spikes.