The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2006

Filed:

Oct. 29, 2003
Applicants:

Christine Hau-riege, Fremont, CA (US);

Amit Marathe, Milpitas, CA (US);

John Sanchez, Jr., Palo Alto, CA (US);

Inventors:

Christine Hau-Riege, Fremont, CA (US);

Amit Marathe, Milpitas, CA (US);

John Sanchez, Jr., Palo Alto, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4163 (2006.01); H01L 21/326 (2006.01); H01L 21/479 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.


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