The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2006

Filed:

Dec. 18, 2002
Applicants:

Jayabrata Ghosh Dastidar, Santa Clara, CA (US);

Adam Wright, Santa Clara, CA (US);

Hung Hing Anthony Pang, San Jose, CA (US);

Binh Vo, San Jose, CA (US);

Ajay Nagarandal, Sunnyvale, CA (US);

Paul J. Tracy, Sunnyvale, CA (US);

Michael Harms, Pleasanton, CA (US);

Inventors:

Jayabrata Ghosh Dastidar, Santa Clara, CA (US);

Adam Wright, Santa Clara, CA (US);

Hung Hing Anthony Pang, San Jose, CA (US);

Binh Vo, San Jose, CA (US);

Ajay Nagarandal, Sunnyvale, CA (US);

Paul J. Tracy, Sunnyvale, CA (US);

Michael Harms, Pleasanton, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.


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